Clock circuits are generally known and used, for example, to generate a clock signal. It is known to connect a clock circuit to a signal processing circuit, which uses the clock signal as a timing signal to perform some kind of signal processing. For example it is known to connect a clock circuit to a pulse-width modulation circuit. The pulse-width modulation circuits may modulate a signal by changing the duty cycle of the signal (that is the period of time the signal has a high value relative to the total period of a signal cycle). The pulse-width modulation may be applied, for example, to convey information over a communications channel or to control the amount of power sent to a load.
However, a problem of clock circuits is that there is a risk that the clock signal is lost by the signal processing circuit. For example, the clock circuit may malfunction or the connection between the clock circuit and the signal processing circuit may be disconnected.
From United States Patent Application Publication US 2005/0206428 a clock generation module is known. The clock generation module includes a redundant clock source which can receive respective timing signals from first and second oscillator devices. The redundant clock source can generate a clock signal from the timing signals. The redundant clock source selects the respective timing signal using clock sense logic and switch logic. The clock sense logic determines signal characteristics of the timing signals and if a timing signal exhibits an undesirable characteristic the switch logics switches to the other timing signal. However, a disadvantage of the clock generation module known form this prior art document is that the local clock signal will exhibit a clock error in case the timing signals deviate from each other, which may for example lead to a loss of data. Also, the clock signal will be lost in case of a malfunction of the redundant clock source itself. Furthermore, the clock generation module includes two oscillator devices, and accordingly is relatively complex and expensive.
From United States Patent Application Publication US 2005/0198549 a data transmission chain is known. The data transmission chain includes two pieces of equipment and a transmission channel between the pieces. Data may be transmitted via the transmission channel. The transmission channel includes a path for the transmission of a clock signal. The piece at the receiving side of the equipment includes a local clock which provides a local clock signal. The local clock signal is used by the receiving side to sample the transmitted date. The local clock signal is periodically synchronised to the transmitted clock signal, that is the leading edge of the local clock signal is shifted to synchronised the local clock signal to the transmitted clock signal. However, a disadvantage of the data transmission chain known from this prior art system is that in case the transmitted clock signal is lost for a longer period of time, the local clock signal cannot be synchronised with the transmitted clock signal and accordingly the local clock signal will exhibit a clock error, which may for example lead to a loss of data.
Accordingly, a common disadvantage of the clock circuits known from the above mentioned prior art documents is that there is a relatively large risk that the clock signal is lost.